The present disclosure relates to integrated circuit (IC) design and, more particularly, to a method, a system and a computer program product for performing a static timing analysis that incorporates the effects of coupled noise between neighboring nets of timing paths in the IC.
In conventional electronic design flow, a designer uses a suite of software design tools to progress from a high level of logical abstraction to a detailed physical representation of an integrated circuit (IC) design that is optimized for manufacture. After defining abstract behavior of the desired IC, the designer translates an abstract logical language to a discrete netlist of logic gates. Based on the netlist of logic gates, the designer uses a cell-based schematic capture tool to generate a bottom-up cell-based schematic of the IC design.
Following the schematic design phase, the cell-based schematic is used to assess the logical functionality of the IC design, but cannot provide an accurate estimate of performance metrics, e.g., timing delays, for a manufacturable IC design. An accurate estimate of the digital and analog performance metrics of the design requires a physical design, including a schematic-driven layout, that exactly places all circuit components and routes all interconnects to minimize timing delays.
Static timing analysis is a method of computing the expected timing delays of digital circuits and determining whether timing constraints required for correct circuit operation are satisfied without requiring computationally intensive simulation. Assessing the ability of a circuit to operate at a specific clock frequency requires the ability to estimate, during the iterative design process, the circuit's delay at many phases of the timing analysis. In particular, delay calculation and timing constraint checking are incorporated into the inner loop of timing analyzers during the placement and routing phases, i.e., the physical design phase, of an IC. While such delay calculations could, in theory, be performed using computationally intensive circuit simulations, in practice, an estimate of the timing delays is provided by methods of static timing analyses that provide reasonably accurate estimates of circuit timing delays.
Static timing analysis may be performed in either a block-based or a path-based manner. Block-based analysis is the most efficient, with a run time that is linear relative to the number of delay elements in the timing graph and computes, for each node in the graph, an arrival time that is the latest or earliest time at which a signal may arrive at the node considering all paths leading to the node. Path-based analyses trace and sum delays along each path through the timing graph or circuit, and determine whether timing constraints on the arrival time at the end of the path are satisfied. Because the number of paths through a circuit grows exponentially with the size of the circuit, path-based analysis is much more computationally expensive than block-based analysis.
Static timing analysis, as well as various other types of analysis of integrated circuit designs, must consider many potential effects. Many of these effects may be considered at different levels of accuracy, with computation costs that increase as the level of accuracy increases. In many cases analysis at a lower level of accuracy may be done in such a way that it produces a pessimist bound on the results that would be produced by the higher accuracy analyses. In such cases, if the potentially pessimistic result produced by a lower accuracy analysis shows that certain portions of the integrated circuit would function correctly, i.e., all timing constraints in those portions would be met in a static timing analysis, an analysis system may avoid employing the higher accuracy and higher computation cost analysis methods on those portions of the design that “passed” the lower accuracy analysis. This general approach may be referred to as variable-detail analysis, and is widely used in static timing analysis.
For example, an initial timing analysis may assume that the entire early and late paths leading to a timing test can vary independently. This can be pessimistic, because portions of those paths may be common, and cannot be both slow in the late mode path and fast in the early mode path. Common path pessimism removal (CPPR), as described in U.S. Pat. No. 5,636,372 which is incorporated into description in its entirety, is a computationally more expensive analysis that can identify these pessimistic cases and produced a more accurate and less pessimistic timing slack for particular timing tests. A variable-detail analysis may apply CPPR methods only to those tests for which the initial less expensive analysis indicated that the timing constraint was not met.
When there is a large amount of pessimism in a low accuracy analysis used as part of a variable-detail analysis system and a large increase in computational cost for the next higher accuracy analysis, it can be beneficial to introduce additional intermediate levels of analysis that can provide reduced pessimism over the low accuracy analysis with less cost than the next higher accuracy analysis.
The method of a static timing analysis can be extended to incorporate the effects of coupled noise on neighboring nets of timing paths in the physical design of the IC. Generally, a circuit will contain many timing paths, where each path extends from a source through a series of nets and gates to a sink. Each gate and net in the design may be included in many different timing paths. A particular net, called a victim net, can be affected by noise from a neighboring net, called an aggressor net. Coupling, e.g., capacitative or inductive coupling, between the aggressor and the victim nets can cause a switching aggressor net to induce an unintentional current, i.e., noise, in the victim net.
When switching times for the aggressor and the victim nets overlap, coupled noise can increase the timing delay, if the aggressor and victim are switching logic levels in opposite directions, and decrease the timing delay, if the aggressor and victim are switching logic levels in the same direction. These increases or decreases in delay due to noise are referred to as delta delays. However, aggressors and victims generally do not switch with every timing cycle and aggressor-switching times may not overlap with victim switching times due to, for example, different triggering paths. It is therefore pessimistic to include the delta delays of all nets in a timing analysis. Methods exist to consider only the N largest delta delays, but they require expensive path-based analysis or multiple parallel block based analyses.
There remains a need to decrease the pessimism of a static timing analysis that estimates the effects of coupled noise on neighboring nets in timing paths of an IC design.